This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2001-318366, filed Oct. 16, 2001; and No. 2002-268190, filed Sep. 13, 2002, the entire contents of both of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device including ferroelectric memory cells.
2. Description of the Related Art
Nonvolatile semiconductor memory devices have recently been widely applied to portable apparatuses, mobile cards, and the like, since the stored data is held in the chips even when no power is supplied.
One of the nonvolatile semiconductor memory devices is a ferroelectric semiconductor memory. The ferroelectric semiconductor memory has the advantage of having higher reading and writing speeds than a flash memory. However, it has disadvantages in that, when a voltage is applied to the ferroelectric capacitor of a memory cell, for example, the amount of polarization decreases, which destroys the stored data. For this reason, when the power supply potential in the chip fluctuates, immediately after the power supply is turned on, for example, the control circuit for the ferroelectric capacitor has to be designed to prevent a voltage from being applied to the capacitor.
The possibility that the stored data will be destroyed becomes stronger when unexpected noise occurs on word lines or plate lines. Therefore, the word-line control circuit and plate-line control circuit have to be especially designed to prevent noise from occurring.
FIG. 14 is a potential waveform diagram of a typical power supply potential waveform in the chip immediately after the power supply for a ferroelectric semiconductor memory is turned on.
In a conventional ferroelectric semiconductor memory, when an external power supply VDD has been turned on and the potential of the external power supply VDD has increased from 0V and reached a certain potential, a plurality of power supply circuits provided for corresponding potentials used in the chip are started at the same time.
FIG. 14 shows a case where, when the potential of the external power supply VDD has reached 3V after the turning on of the external power supply VDD, a VPP power supply circuit and a VINT power supply circuit are started at the same time. When the VPP power supply circuit and VINT power supply circuit have been started simultaneously, the potentials of the internal power supplies VPP, VINT start to rise toward their setting potentials at the same time. One example of the setting potential of the internal power supply VPP is 4V. One example of the setting potential of the internal power supply VINT is 2.5V.
FIG. 15 is a block diagram showing a typical configuration of a ferroelectric semiconductor memory.
As shown in FIG. 15, a VPP power supply circuit 102 generates an internal power supply VPP. The internal power supply VPP is supplied to the word lines and a word-line control circuit 104 that controls the word lines.
A VINT power supply circuit 103 generates an internal power supply VINT. The internal power supply VINT is supplied to the plate lines, a plate-line control circuit 105 that controls the plate lines, and a logic circuit group that controls the operation of the entire chip, for example, a timing control circuit 106.
The timing control circuit 106 outputs a WL activating signal and a PL activating signal. The WL activating signal is supplied to the word-line control circuit 104. The PL activating signal is supplied to the plate-line control circuit 105.
The word-line control circuit 104, which is activated on the basis of, for example, the WL activating signal, controls the potential of the word lines. Before being supplied to the word-line control circuit 104, the WL activating signal passes through a potential amplitude converting circuit LS. The reason for this is that the timing control circuit 106 operates from the internal power supply VINT and the word-line control circuit 104 operates from the internal power supply VPP. That is, the word-line control circuit 104 does not operate properly unless the potential amplitude of the WL activating signal is converted into the potential amplitude of the internal power supply VPP. FIG. 16 shows a circuit diagram of the potential amplitude converting circuit LS.
The plate-line control circuit 105, which is activated on the basis of, for example, the PL activating signal, controls the potential of the plate lines.
A power supply turning-on sensing circuit 101 senses that the external power supply VDD has been turned on and outputs a power supply starting signal. The power supply starting signal is supplied to the VPP power supply circuit 102 and VINT power supply circuit 103.
The VPP power supply circuit 102 and VINT power supply circuit 103 are started simultaneously on the basis of the power supply starting signal. When the VPP power supply circuit 102 and VINT power supply circuit 103 have been started simultaneously, the potential of the internal power supply VPP and the potential of the internal power supply VINT rise at the same time, as shown in FIG. 7.
The power supply turning-on sensing circuit 101 also senses that the external power supply VDD has been turned on and outputs a reset signal RST. The reset signal RST is supplied to each of the word-line control circuit 104, plate-line control circuit 105, and timing control circuit 106. While the reset signal RST is being supplied to those circuits, the word lines and plate lines are inhibited from being activated.
The reset signal RST is cancelled when the internal power supplies VPP, VINT reach to their setting potential, for example, VPP is 4V and VINT is 2.5V. After the reset signal RST has been cancelled, the word lines and plate lines can be activated, which allows the ferroelectric memory cells arranged in the memory cell array to be accessed.
When the internal power supplies VPP, VINT are started from 0V, unexpected noise might occur in the logic circuits to which the power supplies VPP, VINT are supplied. The logic circuits are those included in, for example, the word-line control circuit 104, plate-line control circuit 104, timing control circuit 106, and the like. FIG. 17A shows an example of such a logic circuit. FIG. 17B is a diagram to help explain the way unexpected noise occurs.
As shown in FIG. 17A, the logic circuit in the example includes an inverter whose input is fixed at 0V and an inverter to which the output of the preceding inverter is input. The internal power supply VINT is supplied to each of these inverters.
Since the input to the logic circuit of FIG. 17A is 0V from a logical viewpoint, the output is always at 0V. Actually, however, the output is indefinite until the potential of the internal power supply VINT has risen above the threshold voltage of the transistors included in the logic circuits. As a result, unexpected noise occurs as shown in FIG. 17B.
If unexpected noise occurs in a ferroelectric memory, there is a possibility that the data stored in the ferroelectric memory cells will be destroyed. FIG. 18 shows the way unexpected noise can destroy the stored data.
In the example of FIG. 18, when unexpected noise as explained in FIG. 17B is applied to a plate line PL, a voltage is applied to the ferroelectric capacitor C of the memory cell.
When a voltage is applied across the ferroelectric capacitor C, the amount of polarization, or the stored data, decreases or is destroyed. From this, it can be seen that unexpected noise degrades the data holding characteristic of the ferroelectric memory seriously.
The same holds true for a series connected TC unit type ferroelectric memory as shown in FIG. 19. That is, the data holding characteristic deteriorates in a series connected TC unit type ferroelectric memory. The TC parallel unit series-connection ferroelectric memory is obtained by connecting a plurality of unit cells in series, each unit cell including a cell transistor T having a source terminal and a drain terminal and a ferroelectric capacitor C inbetween the two terminals.
To suppress the generation of unexpected noise, the logic circuit shown in FIG. 17A should be replaced with, for example, a logic circuit as shown in FIG. 20A.
As shown in FIG. 20A, the logic circuit is such that a circuit 200 that fixes the output of the logic circuit at a certain potential is added to the last stage of the logic circuit of FIG. 17A. The circuit 200 fixes the output of the logic circuit at a certain potential, for example, an in-circuit ground potential VSS, on the basis of a reset signal RST. The reset signal RST has a potential higher the internal power supply VINT, such as the potential of the external power supply VDD. In this example, while the reset signal RST of the VDD level is being input, the output of the logic circuit is always fixed at the ground potential GND, or 0V, as shown in FIG. 20B. When the internal power supply VINT rises above the threshold voltage of the transistors and there is no possibility of faulty operations, the reset signal RST may be cancelled, or connected to, for example, ground potential GND.
As described above, for example, the circuit 200 that fixes the output of the logic circuit on the basis of the reset signal RST is added to the last stage of the logic circuit, thereby preventing unexpected noise from occurring when the power supply is turned on. Then, the circuit 200 is built in, for example, the last logic stage of the plate-line driving circuit included in the plate-line control circuit 105. This enables the factor degrading the data holding characteristic due to unexpected noise to be suppressed in the ferroelectric memory.
One known ferroelectric memory controls the internal chip enable signals CE and ICE in response to the external chip enable signal /XCE and power state sense signal POFFL, thereby suppressing memory access to protect the data stored in the ferroelectric memory from being damaged as disclosed in U.S. Pat. No. 5,943,257 (for example, column 11, line 19 to column 13, line 6, FIG. 10 and FIG. 11).
However, there are a good many plate-line driving circuits in the chip. Therefore, incorporating the circuits 200 in the plate-line driving circuits increases the size of the circuit, resulting in an increase in the chip area.
A semiconductor intergraded circuit device according to a first aspect of the present invention comprises: a series connected TC unit type ferroelectric memory which includes series connected memory cells each having a cell transistor having a source terminal and a drain terminal and a ferroelectric capacitor inbetween the two terminals; a first power supply circuit which generates a first power supply potential supplied to the gate of the cell transistor when the cell transistor is in a standby state; and a second power supply circuit which generates a second power supply potential supplied to the source or drain of the cell transistor and starts operating following the start-up of the first power supply circuit after a power supply is turned on.
A semiconductor integrated circuit device according to a second aspect of the present invention comprises: a ferroelectric memory cell which includes a cell transistor and a capacitor; a power supply circuit which generates a power supply potential supplied to the source or drain of the cell transistor; a power supply turning-on sensing circuit which senses the turning on of the power supply and outputs a starting signal to start the power supply circuit; and a delay circuit which delays the starting signal and supplies the delayed signal to the power supply circuit.
A semiconductor integrated circuit device according to a third aspect of the present invention comprises: a ferroelectric memory cell which includes a cell transistor and a capacitor; and a power supply circuit which generates a power supply potential supplied to the source or drain of the cell transistor and which starts operating in a state where the cell transistor is conducting after a power supply is turned on.
A semiconductor integrated circuit device according to a fourth aspect of the present invention comprises: a series connected TC unit type ferroelectric memory which includes series connected memory cells each having a cell transistor having a source terminal and a drain terminal and a ferroelectric capacitor inbetween the two terminals; a first power supply circuit which generates a first power supply potential supplied to the gate of the cell transistor when the cell transistor is in a standby state; and a second power supply circuit which generates a second power supply potential supplied to the source or drain of the cell transistor and starts being deactivated before the first power supply circuit is deactivated after a power supply is turned off.
A semiconductor intergraded circuit device according to a fifth aspect of the invention, comprises: a series connected TC unit type ferroelectric memory which includes series connected memory cells each having a cell transistor having a source terminal and a drain terminal and a ferroelectric capacitor inbetween the two terminals; a first power supply circuit which generates a first power supply potential supplied to the gate of the cell transistor when the cell transistor is in a standby state; and a second power supply circuit which generates a second power supply potential supplied to the source or drain of the cell transistor and which starts operating following the start-up of the first power supply circuit after a power supply is turned on and starts being deactivated before the first power supply circuit is deactivated after the power supply is turned off.